1. Technical Field
Various embodiments of the present disclosure may generally relate to nonvolatile memory devices and, more particularly, to nonvolatile memory devices relating to a wide operation range in a read mode and dully operating against variation of characteristics of transistors.
2. Related Art
Semiconductor memory devices are typically categorized as either random access memory (RAM) devices or read only memory (ROM) devices according to data volatility of the semiconductor memory devices. The RAM devices lose data stored within when the power supplies of the RAM devices are interrupted. In contrast, the ROM devices retain data stored within even when the power supplies of the ROM devices are interrupted. The ROM devices may also be classified as programmable ROM (PROM) devices or mask ROM devices according to data input methods, that is, data program methods. The PROM devices may be fabricated and sold out without program and may be directly programmed by customers (i.e., users) after fabrication of the PROM devices. The mask ROM devices may be programmed during fabrication thereof using implantation masks manufactured based on data requested by users. The PROM devices may include one-time PROM (OTPROM) devices, erasable PROM (EPROM) devices and electrically erasable PROM (EEPROM) devices. Once the OTPROM devices are programmed, the programmed data of the OTPROM devices cannot be changed.
N-MOS transistors or P-MOS transistors may be used as cell transistors of the nonvolatile memory devices, for example, the OTPROM devices. If P-MOS transistors are used as the cell transistors of the nonvolatile memory devices, the P-MOS cell transistors may have a turn-off status as an initial status of the P-MOS cell transistors and may have a turn-on status as a programmed status of the P-MOS cell transistors. A read operation of the P-MOS cell transistors may be executed by sensing a voltage level of a bit line connected to any one selected from the P-MOS cell transistors. In such a case, the voltage level of the bit line may be determined by a resistance ratio of an equivalent resistance of the selected P-MOS cell transistor to a resistance value of a load resistor coupled between a supply voltage line and the bit line.